![]() Writes an interrupt number to set the interrupt's pending status (Armv8-M Mainline only)Īll these registers, with the exception of the Software Trigger Interrupt Register (STIR), are only accessible at privileged level. In Armv8-M Baseline, each IPR register is 32-bit (contains priority levels for four interrupts). In Armv8-M Mainline, each IPR register is 8 bits. Interrupt Priority Level for each interrupt Write 1 to set an interrupt to Non-secure, clear to 0 to set an interrupt as Secure Interrupt Target Non-secure State Registers Uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) // Get the pending status of an interrupt Read more Navigate Down ![]() Void NVIC_ClearPendingIRQ(IRQn_Type IRQn) // Clear the pending status of an interrupt Void NVIC_SetPendingIRQ(IRQn_Type IRQn) // Set the pending status of an interrupt The CMSIS-Core provides the following functions for accessing Interrupt Pending registers: Write 1 to clear bit to 1 write 0 has no effect Read value indicates the current pending statusĬlear pending for external interrupt #32–63Ĭlear pending for external interrupt #64–95 Write 1 to clear bit to 0 write 0 has no effect ![]() ![]() Write 1 to set bit to 1 write 0 has no effectĬlear pending for external interrupt #0–31
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